Nonvolatile semiconductor device and method of manufacturing the same

ABSTRACT

A method and apparatus of forming a nonvolatile semiconductor device including forming a first gate insulating film on a main surface of a first semiconductor region, forming a first gate electrode on the first gate insulating film, forming a second gate insulating film, forming a second gate electrode over a first side surface of the first gate electrode, selectively removing the second gate insulating film, etching the second gate insulating film kept between the second gate electrode and a main surface of the first semiconductor region in order to form an etched charge storage layer, introducing first impurities in the first semiconductor region in a self-aligned manner to the second gate electrode in order to form a second semiconductor region, annealing the semiconductor substrate to extend the second semiconductor region to an area under the second gate electrode.

CROSS-REFERENCE TO RELATED APPLICATION

This is a continuation application of U.S. Ser. No. 13/755,348, filedJan. 31, 2013, which is a continuation of U.S. Ser. No. 12/188,412,filed Aug. 8, 2008 (now U.S. Pat. No. 8,390,053), which claims priorityfrom Japanese Patent Application No. JP 2007-218147 filed on Aug. 24,2007, the content of all are hereby incorporated by reference into thisapplication.

TECHNICAL FIELD OF THE INVENTION

The present invention relates to a semiconductor device and amanufacturing technology thereof. More particularly, the presentinvention relates to a technology effectively applied to a semiconductordevice having a MONOS (Metal Oxide Nitride Oxide Semiconductor) memorycell or an NROM memory cell that uses a nitride film as a charge storagelayer.

BACKGROUND OF THE INVENTION

Embedding a nonvolatile memory cell and a logic semiconductor devicetogether on the same silicon substrate allows obtaining ahigh-performance semiconductor device. These semiconductor devices arewidely used for industrial machines, household appliances, devicesmounted on vehicles, and the like as an incorporated type microcomputer.Generally, a program needed for the microcomputer is stored in thenonvolatile memory embedded together, and is read for use as necessary.

In nonvolatile memory cells in practical use today, field effecttransistors for storage are used, in which a threshold voltage varieswith accumulation of an electric charge. The electric charge holdingsystem of the field effect transistor for storage includes the floatinggate system (refer to Japanese Patent Application Laid-Open PublicationNo. H05-121700 (Patent Document 1), for example) that stores an electriccharge in a conductive material electrically isolated, and the MONOSsystem (refer to Japanese Patent Application Laid-Open Publication No.H05-048113 (Patent Document 2), for example) that stores electriccharges in an insulator, such as a silicon nitride film, with a propertyto accumulate an electric charge.

The floating gate system has good characteristics for holding anelectric charge, and widely used for flash memories for storing programsin cellular phones and large capacity flash memories for storing data,etc. However, maintenance of the capacitive coupling ratio needed forthe potential control of the floating gate is increasingly complex withfiner design rules, and memory cell structures are becoming morecomplicated. In addition, the thickness of an oxide film surrounding thefloating gate must be 8 nm or more to control the leakage of a holdingelectric charge, the limit of the finer design rules aiming at highspeed and high integration is approaching. Since the electric charge isstored in the conductive material, a single defect that could be aleakage path in the oxide film around the floating gate extremelyshorten a period for holding an electric charge.

On the other hand, the MONOS system generally has poor characteristicsfor holding an electric charge than the floating gate system, and thethreshold voltage tends to drop logarithmically with time. Therefore,although the MONOS system has been known for many years, only a smallportion of products has used the system in practical use. However, sincethe MONOS system uses a discrete storage system that stores the electriccharge in the insulator, existence of some leakage paths does not causeall the holding electric charge to be lost, and the MONOS system isadvantageously tolerant to a defect of an oxide film surrounding theinsulator. Therefore, the MONOS system has been paid attention to inrecent years with the advancement of finer design rules. Since a thinoxide film of 8 nm or less can be applied, the system is suitable forfiner design rules, reliability can be easily estimated since the timefor holding an electric charge is not extremely shortened by a defectthat happens with low probability, and the memory cell structure issimple and the system can be easily embedded together with a logiccircuit section.

The simplest memory cell with the MONOS system includes the NROMstructure (refer to U.S. Pat. No. 5,768,192 (Patent Document 3), andJapanese Patent Application Laid-Open Publication No. 2004-186452(Patent Document 4), for example). This structure replaces the gateinsulating film of the field effect transistor with the ONO filmstructure comprising an oxide film/nitride film/oxide film, and the CHE(Channel Hot Electron) system is used for writing, and the BTBT(Band-To-Band Tunneling) system with the interband tunneling is used forerasing. Simple formation processes thereof makes the system suitablefor finer design rules and embedding together with the logic circuitsection.

Another memory cell suitable for embedding together with a logic circuitsection includes a split-gate type memory cell comprising a field effecttransistor for selection, and a field effect transistor for a memory.This memory cell is suitable for embedding together because a fasterwriting operation and a smaller power supply can be provided with theSSI (Source Side Injection) system having good injection efficiency, andbecause the area of a peripheral circuit can be reduced since thetransistor that selects this memory cell and the transistor connectedthereto can be constituted with a transistor of a low voltage systemwith a small device area.

A split-gate type memory cell especially suitable for finer design rulesincludes a memory cell with a structure that forms one of the fieldeffect transistors with a sidewall using self aligning (refer toJapanese Patent Application Laid-Open Publication No. H05-121700 (PatentDocument 1), for example). In this case, since the alignment margin forphotolithography is unnecessary, and the gate length of the field effecttransistor formed with self aligning can be equal to or smaller than theminimum resolution dimension of the photolithography, a memory cell withdesign rules finer than a conventional memory cell in which the fieldeffect transistor for selection and the field effect transistor for thememory are respectively formed with a photomask can be achieved.

SUMMARY OF THE INVENTION

The inventors have examined the structure of a memory cell to provideimprovements etc. in the rewrite (writing/erasing) endurance and in dataretention characteristic of a split-gate type memory cell. However, therewrite endurance of the split-gate type memory cell includes varioustechnical problems described hereinafter.

When the split-gate type memory cell is held in a write state at a hightemperature, the threshold voltage of the memory cell graduallydecreases as the holding time passes.

FIG. 44 shows an example of characteristics for holding the memory cellat a high temperature in the write state after the writing was performedin the SSI system and erasing was performed in the BTBT system,resulting in rewriting of 10K times. The horizontal axis of the graphchart of FIG. 44 indicates the time passed in the write state afterrewriting was performed 10K times and then the memory cell was turned tothe write state, and the vertical axis of the graph charts of FIG. 44indicates varied amount of the threshold voltage of the memory cell.Conditions for writing and erasing in the memory cell are the same asthe one in FIG. 4 described hereinafter. Verification was performedunder the conditions for writing and erasing to measure the thresholdvoltage after a write judgment was configured as 4 volts and an erasejudgment was configured as −1.8 volts, rewriting was performed 10Ktimes, and a high temperature was held in the write state. The variationof the threshold voltage was worst when the high temperature was held,and when the threshold voltage was not more than a judgment standard,correct “0” or “1” judgment was impossible.

As shown in FIG. 44, the threshold voltage of the memory cell graduallydecreases as the time holding a high temperature passes. Reasons for thevariation of the threshold voltage include electrons and holes locallyexisting in the charge storage layer moving in the transverse directionto be vanished, the recovery of interface states, and the electrons inthe charge storage layer detrapped in the silicon substrate.

FIG. 45 shows a relative ratio between the varied amounts of thethreshold voltage after each holding voltage was applied to the memorygate electrode and held at a high temperature for 1 hour, and the variedamounts of the threshold voltage after the holding voltage of 0 volts isapplied to the memory gate electrode and held at a high temperature for1 hour. The component accelerated by the holding voltage applied to thememory gate electrode is a component of the detrap mentioned above. Asshown in FIG. 45, the relative value of the varied amount of thethreshold voltage is the smallest when the holding voltage is +3 volts,and the relative value of approximately 93% is a component that is notaccelerated by the holding voltage, that is, the component other thandetrap. Therefore, approximately 90% or more of the varied amount of thethreshold voltage when the holding voltage is 0 volt is considered to bea component that vanishes by the electrons and the holes locallyexisting in the charge storage layer moving in the transverse direction.

In addition, when the split-gate type memory cell is held in an erasestate at room temperature, the threshold voltage of the memory cellgradually increases as the holding time passes.

FIG. 46 shows an example of characteristics for holding the memory cellat room temperature in the erase state after writing was performed inthe SSI system and erasing is performed in the BTBT system, resulting inrewriting of 10K times. The horizontal axis of the graph chart of FIG.45 indicates the time passed in the erase state after rewriting wasperformed 10K times and then the memory cell was turned to the erasestate, and the vertical axis of the graph charts of FIG. 46 indicatesvaried amount of the threshold voltage of the memory cell. Conditionsfor writing and erasing in the memory cell are the same as the one inFIG. 4 described hereinafter. Verification was performed under theconditions for writing and erasing to measure the threshold voltageafter the write judgment was configured as 4 volts and the erasejudgment was configured as −1.8 volts, rewriting was performed 10Ktimes, and the room temperature was held in the erase state.

As shown in FIG. 46, the threshold voltage of the memory cell graduallyincreases as the time holding the room temperature passes. One of thereasons for the variation of the threshold voltage is considered to becoupling of the electrons and the holes injected in the charge storagelayer after the electrons in the silicon substrate are injected into thecharge storage layer via a defect of the oxide film in the siliconsubstrate side produced by rewriting. Strong acceleration of theelectric field on the main surface of the silicon substrate in thevertical direction allows easy injection of the electrons and couplingof the electrons and the holes.

An object of the present invention is to provide a technology forimproving data retention characteristics of nonvolatile memories storingan electric charge in an insulator.

The above and other objects and novel characteristics of the presentinvention will be apparent from the description of this specificationand the accompanying drawings.

The typical ones of the inventions disclosed in this application will bebriefly described as follows.

A nonvolatile semiconductor device of the present invention comprises: afield effect transistor comprising an insulating film with a laminatedstructure with a bottom-layer insulating film, a charge storage layercapable of accumulating an electric charge, and a top-layer insulatingfilm formed in turn on the main surface of the semiconductor substratefrom the lowest layer, a gate electrode formed on the insulating film,and a source region formed in the semiconductor substrate under one sideof the gate electrode, in which an overlapping amount of the chargestorage layer and the source region is less than 40 nm.

A method of manufacturing a nonvolatile semiconductor device of thepresent invention is a method of manufacturing a nonvolatilesemiconductor device having a field effect transistor provided with ancapability for holding an electric charge, the method comprising thesteps of: forming a bottom-layer insulating film, a charge storage layercapable of accumulating an electric charge, and a top-layer insulatingfilm in turn on the main surface of the semiconductor substrate from thelowest layer; forming a gate electrode on the top-layer insulating film;etching a specified amount of the charge storage layer from a side ofthe gate electrode; forming an impurity region in the semiconductorsubstrate under one side of the gate electrode by ion-implanting animpurity to the semiconductor substrate using the gate electrode as amask; and forming a source region by activating the impurity region withheat-treating the semiconductor substrate, in which an overlappingamount of the charge storage layer and the source region is less than 40nm.

A method of manufacturing a nonvolatile semiconductor device of thepresent invention is a method of manufacturing a nonvolatilesemiconductor device having a field effect transistor provided with ancapability for holding an electric charge, the method comprising thesteps of: forming a bottom-layer insulating film, a charge storage layercapable of accumulating an electric charge, and a top-layer insulatingfilm in turn on a main surface of the semiconductor substrate from thelowest layer; forming a gate electrode on the top-layer insulating film;forming a sidewall on a side wall of the gate electrode; forming animpurity region in the semiconductor substrate under one side of thegate electrode by ion-implanting an impurity to the semiconductorsubstrate using the gate electrode and the sidewall as a mask; andforming a source region by activating the impurity region withheat-treating the semiconductor substrate, in which an overlappingamount of the charge storage layer and the source region is less than 40nm.

The effects obtained by typical aspects of the present invention will bebriefly described below.

A nonvolatile memory using a charge accumulation film represented by aMONOS type nonvolatile memory has a smaller variation of the thresholdvoltage when a high temperature is held in the write state, and asmaller variation of the threshold voltage when the room temperature isheld in the erase state, resulting in an improved data retentioncharacteristic.

BRIEF DESCRIPTIONS OF THE DRAWINGS

FIG. 1 is an array configuration using a split-gate type MONOS memorycell according to Embodiment 1 of the present invention;

FIG. 2 is a plan view showing a layout of the split-gate type MONOSmemory cell according to Embodiment 1 of the present invention;

FIG. 3 is a cross-sectional view of main parts of the memory cell of thesplit-gate type MONOS memory cell according to Embodiment 1 of thepresent invention, and a channel is cut in the direction intersectingthe memory gate electrode;

FIG. 4 is a table summarizing an example of conditions for applying thevoltage to each part of the split-gate type MONOS memory cell duringwrite, erase, and read operations according to Embodiment 1 of thepresent invention;

FIG. 5 is a cross-sectional view of main parts of the split-gate typeMONOS memory cell for describing the write operation according toEmbodiment 1 of the present invention;

FIG. 6 is a cross-sectional view of main parts of the split-gate typeMONOS memory cell for describing the erase operation according toEmbodiment 1 of the present invention;

FIG. 7 is a cross-sectional view of main parts showing an enlarged partof the split-gate type MONOS memory cell according to Embodiment 1 ofthe present invention;

FIG. 8 is a graph chart showing the characteristics for holding at ahigh temperature of the split-gate type MONOS memory cell in the writingstate after rewriting 10K times according to Embodiment 1 of the presentinvention;

FIG. 9 is a graph chart showing the characteristics for erasing at roomtemperature of the split-gate type MONOS memory cell after rewriting 10Ktimes according to Embodiment 1 of the present invention;

FIG. 10 is a cross-sectional view of main parts of the split-gate typeMONOS memory cell during the manufacturing process according toEmbodiment 1 of the present invention;

FIG. 11 is a cross-sectional view of main parts of the memory cell shownin FIG. 10 during the manufacturing process after the process of FIG.10;

FIG. 12 is a cross-sectional view of main parts of the memory cell shownin FIG. 10 during the manufacturing process after the process of FIG.11;

FIG. 13 is a cross-sectional view of main parts of the memory cell shownin FIG. 10 during the manufacturing process after the process of FIG.12;

FIG. 14 is a cross-sectional view of main parts of the memory cell shownin FIG. 10 during the manufacturing process after the process of FIG.13;

FIG. 15 is a cross-sectional view of main parts of the memory cell shownin FIG. 10 during the manufacturing process after the process of FIG.14;

FIG. 16 is a cross-sectional view of main parts of the memory cell shownin FIG. 10 during the manufacturing process after the process of FIG.15;

FIG. 17 is a graph chart showing the relation between the etching amountof the charge storage layer and the etching time according to Embodiment1 of the present invention;

FIG. 18 is a cross-sectional view of main parts of the memory cell shownin FIG. 10 during the manufacturing process after the process of FIG.16;

FIG. 19 is a cross-sectional view of main parts of the memory cell shownin FIG. 10 during the manufacturing process after the process of FIG.18;

FIG. 20 is a cross-sectional view of main parts of the memory cell shownin FIG. 10 during the manufacturing process after the process of FIG.19;

FIG. 21 is a cross-sectional view of main parts of the memory cell shownin FIG. 10 during the manufacturing process after the process of FIG.20;

FIG. 22 is a cross-sectional view of main parts of the memory cell shownin FIG. 10 during the manufacturing process after the process of FIG.21;

FIG. 23 is a cross-sectional view of main parts of the memory cell shownin FIG. 10 during the manufacturing process after the process of FIG.22;

FIG. 24 is a cross-sectional view of main parts of the split-gate typeMONOS memory cell during the manufacturing process according toEmbodiment 2 of the present invention;

FIG. 25 is a cross-sectional view of main parts of the memory cell shownin FIG. 24 during the manufacturing process after the process of FIG.24;

FIG. 26 is a cross-sectional view of main parts of the memory cell shownin FIG. 24 during the manufacturing process after the process of FIG.25;

FIG. 27 is a cross-sectional view of main parts of the memory cell shownin FIG. 24 during the manufacturing process after the process of FIG.26;

FIG. 28 is a cross-sectional view of main parts of the memory cell shownin FIG. 24 during the manufacturing process after the process of FIG.27;

FIG. 29 is a cross-sectional view of main parts of the memory cell shownin FIG. 24 during the manufacturing process after the process of FIG.28;

FIG. 30 is a graph chart showing the characteristics for holding at ahigh temperature of the memory cell in the writing state after rewriting10K times according to Embodiment 2 of the present invention;

FIG. 31 is a cross-sectional view of main parts of a first example ofthe split-gate type MONOS memory cell during the manufacturing processaccording to Embodiment 3 of a present invention;

FIG. 32 is a cross-sectional view of main parts of the memory cell shownin FIG. 31 during the manufacturing process after the process of FIG.31;

FIG. 33 is a cross-sectional view of main parts of a second example ofthe split-gate type MONOS memory cell during the manufacturing processaccording to Embodiment 3 of the present invention;

FIG. 34 is a cross-sectional view of main parts of the memory cell shownin FIG. 33 during the manufacturing process after the process of FIG.33;

FIG. 35 is a graph chart showing the characteristics for holding at roomtemperature of the memory cell in the erase state after rewriting 10Ktimes according to Embodiment 3 of the present invention;

FIG. 36 is a cross-sectional view of main parts of the first example ofthe NROM memory cell during the manufacturing process according toEmbodiment 4 of the present invention;

FIG. 37 is a cross-sectional view of main parts of the memory cell shownin FIG. 36 during the manufacturing process after the process of FIG.36;

FIG. 38 is a cross-sectional view of main parts of the memory cell shownin FIG. 36 during the manufacturing process after the process of FIG.37;

FIG. 39 is a cross-sectional view of main parts of the memory cell shownin FIG. 36 during the manufacturing process after the process of FIG.38;

FIG. 40 is a cross-sectional view of main parts of the memory cell shownin FIG. 36 during the manufacturing process after the process of FIG.39;

FIG. 41 is a table summarizing an example of conditions for applying thevoltage to each part of the NROM memory cell during write, erase, andread operations according to Embodiment 4 of the present invention;

FIG. 42 is a cross-sectional view of main parts of the second example ofthe NROM memory cell during the manufacturing process according toEmbodiment 4 of the present invention;

FIG. 43 is a cross-sectional view of main parts of the memory cell shownin FIG. 42 during the manufacturing process after the process of FIG.42;

FIG. 44 is a graph chart showing an example of the characteristics forholding at a high temperature of the memory cell in the write stateafter writing is performed in the SSI system and erasing is performed inthe BTBT system, resulting in rewriting of 10K times;

FIG. 45 is a graph chart showing a relative ratio between the variedamounts of the threshold voltage after each holding voltage is appliedto the memory gate electrode and held at a high temperature for 1 hour,and the varied amounts of the threshold voltage after the holdingvoltage of 0 volt is applied to the memory gate electrode and held at ahigh temperature for 1 hour; and

FIG. 46 is a graph chart showing an example of the characteristics forholding at room temperature of the memory cell in the erase state afterwriting is performed in the SSI system and erasing is performed in theBTBT system, resulting in the rewriting of 10K times.

DESCRIPTIONS OF THE PREFERRED EMBODIMENTS

In the embodiments described below, the invention will be described in aplurality of sections or embodiments when required as a matter ofconvenience. However, these sections or embodiments are not irrelevantto each other unless otherwise stated, and the one relates to the entireor a part of the other as a modification example, details, or asupplementary explanation thereof.

Also, in the embodiments described below, when referring to the numberof elements (including number of pieces, values, amount, range, and thelike), the number of the elements is not limited to a specific numberunless otherwise stated or except the case where the number isapparently limited to a specific number in principle. The number largeror smaller than the specified number is also applicable.

Further, in the embodiments described below, it goes without saying thatthe components (including element steps) are not always indispensableunless otherwise stated or except the case where the components areapparently indispensable in principle.

Similarly, in the embodiments described below, when the shape of thecomponents, positional relation thereof, and the like are mentioned, thesubstantially approximate and similar shapes and the like are includedtherein unless otherwise stated or except the case where it can beconceived that they are apparently excluded in principle. The same goesfor the numerical value and the range described above.

Further, in the embodiments described below, MIS-FET (Metal InsulatorSemiconductor Field Effect Transistor) representing a field-effecttransistor is abbreviated as MIS, and an n-channel type MIS-FET isabbreviated as nMIS. MOSFET (Metal Oxide Semiconductor FET) is afield-effect transistor with a gate insulating film thereof formed of(comprising) a silicon oxide (SiO₂ and the like) film, and is containedin the subordinate concept of the MIS. In addition, needless to say, anMONOS type memory cell indicated in this embodiment is also contained inthe subordinate concept of the MIS. In addition, silicon nitride in theembodiments includes not only Si₃N₄, but also insulating films ofsimilar composition made of nitride of silicon. In addition, a wafer inthe embodiments indicate mainly an Si (Silicon) single crystal wafer, aswell as an SOI (Silicon On Insulator) wafer, an insulating filmsubstrate for forming an integrated circuit thereon etc. Shapes thereofinclude not only a circle and a nearly circle, but also a square, arectangle and the like.

Further, components having the same function are denoted by the samereference symbols throughout the drawings for describing the embodiment,and the repetitive description thereof will be omitted. Hereinafter,embodiments of the present invention will be described in detail withreference to the accompanying drawings.

Embodiment 1

An example of the structure of a split-gate type MONOS memory cellaccording to Embodiment 1 will be described with reference to FIGS. 1 to3. FIG. 1 is an array configuration using the split-gate type MONOSmemory cell; FIG. 2 shows a plan view showing a layout of the split-gatetype MONOS memory cell; and FIG. 3 is a cross-sectional view of mainparts of the memory cell, and a channel is cut in the directionintersecting the memory gate electrode.

As shown in FIGS. 1 and 2, there are two types of word lines includingword lines MG1 and MG2 for a memory gate electrode MG of an nMIS (Qnm)for a memory, and word lines CG1, CG2, CG3, and CG4 for a selection gateelectrode CG of an nMIS (Qnc) for selection, which are extended inparallel in a first direction. Source lines SL1 and SL2 are extended inthe first direction in parallel with the word lines, are adjacent to thememory gate electrode MG of each memory cell, and are connected with thesource region shared with the memory cell in opposite. In addition, bitlines BL1 and BL2 are extended in a second direction intersecting theword lines extended in the first direction, and connected with a drainregion adjacent to the selection gate electrode CG of each memory cell.A unit memory cell MC is located in the area surrounded by the dottedline in FIG. 2, and is electrically insulated from an adjacent memorycell by a device isolation portion SGI.

As shown in FIG. 3, the semiconductor substrate 1 includes, for example,a p-type single crystal silicon, and an nMIS (Qnc) for selection and annMIS (Qnm) for the memory of a memory cell MC1 according to Embodiment 1are located in an active region of the main surface (device formingface). A drain region Drm and a source region Srm of this memory cellMC1 have, for example, n⁻-type semiconductor regions 2 ad and 2 as witha relatively low concentration, and an n⁺-type semiconductor region 2 bwith a relatively high concentration with an impurity concentrationhigher than the n⁻-type semiconductor regions 2 ad and 2 as (LDD(Lightly Doped Drain) structure). The n⁻-type semiconductor regions 2 adand 2 as are located on a channel region side of the memory cell MC1,and the n⁺-type semiconductor region 2 b is located in a positiondistant from the channel regions side of the memory cell MC1 by thedistance of the n⁻-type semiconductor regions 2 ad and 2 as.

On the main surface of the semiconductor substrate 1 between the drainregion Drm and the source region Srm, the selection gate electrode CG ofthe nMIS (Qnc) for selection and the memory gate electrode MG of thenMIS (Qnm) for the memory are adjacently extended, and in the extendingdirection, a plurality of memory cells MC1 are adjacent to each othervia the device isolation portion SGI formed on the semiconductorsubstrate 1. The selection gate electrode CG is located in a first areaof the main surface of the semiconductor substrate 1, and the memorygate electrode MG is located in a second area different from the firstarea of the main surface of the semiconductor substrate 1. The selectiongate electrode CG is formed of, for example, an n-type polycrystallinesilicon film, and the selection gate electrode CG has an impurityconcentration of, e.g., approximately 2×10²⁰ cm⁻³, and has a gate lengthof, e.g., 100 to 200 nm. The memory gate electrode MG is formed of,e.g., an n-type polycrystalline silicon film and has an impurityconcentration of, for example, approximately 2×10²⁰ cm⁻³ and has a gatelength of, e.g., 50 to 150 nm.

On the top surface of the selection gate electrode CG, the memory gateelectrode MG, and the n⁺-type semiconductor region 2 b constituting apart of the source region Srm and the drain region Drm, a silicide layer3 such as cobalt silicide, nickel silicide, and titanium silicide, andthe like is formed. The MONOS type memory cell needs to supply electricpotential to the selection gate electrode CG and the memory gateelectrode MG, and an operating speed thereof greatly depends on theresistance of the selection gate electrode CG and the memory gateelectrode MG. Therefore, the resistance of the selection gate electrodeCG and the memory gate electrode MG is preferably lowered by forming thesilicide layer 3. The thickness of the silicide layer 3 is approximately20 nm, for example.

Between the selection gate electrode CG and the main surfaces of thesemiconductor substrate 1, a gate insulating film 4 formed of a thinsilicon oxide film with a thickness of approximately 1 to 5 nm isformed. Therefore, the selection gate electrode CG is located on thedevice isolation portion SGI and on the first area of the semiconductorsubstrate 1 via the gate insulating film 4. For example, boron isintroduced to form a p-type semiconductor region 5 on the main surfaceof the semiconductor substrate 1 under the gate insulating film 4. Thesemiconductor region 5 is a semiconductor region for forming a channelof the nMIS (Qnc) for selection, and the semiconductor region 5configures the threshold voltage of the nMIS (Qnc) for selection to aspecified value.

The memory gate electrode MG is provided on one side of the side wall ofthe selection gate electrode CG, and the insulating film for holding theelectric charge (hereinafter described as insulating films 6 b, 6 t, anda charge storage layer CSL) that is laminated with an insulating film 6b, a charge storage layer CSL, and an insulating film 6 t insulates theselection gate electrode CG from the memory gate electrode MG. Inaddition, the memory gate electrode MG is located on the second area ofthe semiconductor substrate 1 via the insulating films 6 b, 6 t, and thecharge storage layer CSL. In FIG. 3, the insulating film 6 b, 6 t, andthe charge storage layer CSL is expressed as 6 b/CSL/6 t.

The charge storage layer CSL is located between the insulating film 6 band 6 t in the vertical direction and formed of, e.g., a silicon nitridefilm and has a thickness of approximately 5 to 20 nm. The siliconnitride film has a discrete trap state in the film, and a capability toaccumulate an electric charge in the trap state. The insulating films 6b and 6 t include a silicon oxide film and the like. The thickness ofthe insulating film 6 b is from approximately 1 to 10 nm, and thethickness of the insulating film 6 t is from approximately 5 to 15 nm.The insulating films 6 b and 6 t can also be formed with a silicon oxidefilm including nitrogen.

Furthermore, the charge storage layer CSL that intervenes between thememory gate electrode MG and the semiconductor substrate 1 is formedshorter than the gate length of the memory gate electrode MG or thelength of the insulating films 6 t and 6 b, and the overlapping amountof the charge storage layer CSL and the source region Srm is controlledto be a specified value. The characteristics of the memory cell MC1described in Embodiment 1 is that the length of the charge storage layerCSL that intervenes between the memory gate electrode MG and thesemiconductor substrate 1 is shorter than the gate length of the memorygate electrode MG or the length of the insulating films 6 t and 6 b, andthe overlapping amount of the charge storage layer CSL and the sourceregion Srm is configured to be a specified value. The size and therewriting (write/erase) characteristics of each of the main parts of thememory cell MC1 including the charge storage layer CSL will be describedwith reference to FIGS. 7 to 9, and the method of manufacturing thememory cell MC1 including the charge storage layer CSL will be describedwith reference to FIGS. 10 to 23 in detail.

An n-type semiconductor region 7 is formed with an introduction of, forexample, arsenic or phosphorus under the insulating film 6 b and on themain surface of the semiconductor substrate 1 between the p-typesemiconductor region 5 and the source region Srm. The semiconductorregion 7 is a semiconductor region for forming the channel of the nMIS(Qnm) for the memory, and the semiconductor region 7 configures thethreshold voltage of the nMIS (Qnm) for the memory to be a specifiedvalue. The drain region Drm is connected via a plug PLG embedded in acontact hole CNT with a first layer interconnection M1 extending in thesecond direction intersecting the memory gate electrode MG (or theselection gate electrode CG) extending in the first direction. Thiswiring M1 constitutes the bit line BL1 and BL2 of each memory cell MC1.

Next, the write, erase, and read method of the split-gate type MONOSmemory cell according to Embodiment 1 will be described with referenceto FIGS. 4 to 6.

FIG. 4 shows an example of conditions for applying the voltage to eachpart of the memory cell MC1 during write, erase, and read operations.FIG. 4 shows a voltage Vd applied to the drain region Drm, a voltage Vcgapplied to the selection gate electrode CG, a voltage Vmg applied to thememory gate electrode MG, a voltage Vs applied to the source region Srm,and a voltage Vsub applied to the semiconductor substrate 1 of thememory cell MC1 mentioned above. The voltages shown in FIG. 4 which areexamples of application conditions are not limited thereto, and thusmodifications are possible if needed. In addition, in Embodiment 1,inject of the electrons to the charge storage layer CSL is defined as“write,” and injection of the holes is defined as “erase.”

FIG. 5 shows a cross-sectional view of main parts of the memory cell MC1for describing the write operation. The source side injecting system ofthe electron (hot electron) called the SSI system can be used as a writemethod. For example, each voltage shown in FIG. 4 is applied to eachpart of the memory cell MC1 to inject the electrons into the chargestorage layer CSL of the memory cell MC1. The electrons are generated inthe channel region (between the source region Srm and the drain regionsDrm) under in between the two gate electrodes (the memory gate electrodeMG and the selection gate electrode CG), and the electrons are locallyinjected in an area on the nMIS (Qnc) for selection side of the chargestorage layer CSL under the memory gate electrode MG. The injectedelectrons are discretely captured by the trap of the charge storagelayer CSL, resulting in a higher threshold voltage of the nMIS (Qnm) forthe memory.

FIG. 6 shows a cross-sectional view of main parts of the memory cell MC1for describing the erasing operation. The BTBT system can be used as theerasing method. For example, each voltage shown in FIG. 4 is applied toeach part of the memory cell MC1 to electrically accelerating the holesgenerated by the interband tunneling phenomenon for injecting anderasing into the charge storage layer CSL. This lowers the thresholdvoltage of the nMIS (Qnm) for the memory.

When reading, for example, the voltages shown in the “Read” column ofFIG. 4 are applied to each part of the memory cell MC1 that performs aread operation. The current flowing in the drain region Drm is measuredwith the voltage Vmg applied to the memory gate electrode MG whenreading as a value between the threshold voltage of the nMIS (Qnm) forthe memory in the write state and the threshold voltage of the nMIS(Qnm) for the memory in the erase state to distinguish the write statefrom the erase state by the size of the current.

Next, the size and the rewriting (write/erase) characteristics of eachof the main part of the split-gate type MONOS memory cell MC1 accordingto Embodiment 1 will be described with reference to FIGS. 7 to 9 indetail. FIG. 7 is a cross-sectional view of main parts showing anenlarged part of the memory cell; FIG. 8 is graph chart showing thecharacteristics for holding at a high temperature of the memory cell inthe writing state after rewriting 10K times; and FIG. 9 is graph chartshowing the characteristics for erasing at room temperature of thememory cell after rewriting 10K times.

The split-gate type MONOS memory cell according to Embodiment 1 isdifferent from the conventional split-gate type MONOS memory cell inthat the charge storage layer CSL that intervenes between the memorygate electrode MG and the semiconductor substrate 1 of the nMIS (Qnm)for the memory is formed shorter than the gate length of the memory gateelectrode MG or the length of the insulating films 6 t and 6 b tocontrol the overlapping amount of the charge storage layer CSL and thesource region Srm to a specified value. The variation of the thresholdvoltage when a high temperature is held in the write state is consideredto be caused mainly by the electrons and holes that locally exist in thecharge storage layer CSL moving in the transverse direction to bevanished, and can be reduced by reducing the holes that are accumulatedin the charge storage layer CSL on the source region Srm and that areproduced by repeating rewriting operations. Therefore, forming a shortercharge storage layer CSL reduces the overlapping amount of the sourceregion Srm and charge storage layer CSL, resulting in smaller variationsof the threshold voltage.

As shown in FIG. 7, the insulating film 6 t, 6 b, and the charge storagelayer CSL intervenes between the memory gate electrode MG and thesemiconductor substrate 1 of the nMIS (Qnm) for the memory. The chargestorage layer CSL overlaps with the charge storage layer CSL and thesource region Srm formed in the semiconductor substrate 1, but it isformed shorter than the gate length (Lg) of the memory gate electrode MGand the insulating films 6 t and 6 b. The overlapping amount (Lono) is,for example, determined by an etching amount of the charge storage layerCSL (Let), and a concentration profile of an n⁻-type semiconductorregion 2 as constituting a part of the source region Srm, and the like.However, since the shape of the n⁻-type semiconductor region 2 as alsoaffects operating characteristics of the memory cell MC1 other than thedata retention characteristic, configuration of forming conditions forthe n⁻-type semiconductor region 2 as is difficult only to maintain thedata retention characteristic; therefore, the overlapping amount (Lono)is mainly controlled by the etching amount (Let) of the charge storagelayer CSL.

FIG. 8 shows the relation between the varied amount of the thresholdvoltage of the memory cell, and the overlapping amount of the chargestorage layer and the source region when a high temperature is held inthe write state for 1 hour after rewriting 10K times. Rewriting of 10Ktimes is performed according to the writing and erasing conditions shownin FIG. 4. The overlapping amount of the charge storage layer and thesource region is adjusted with the etching amount of the charge storagelayer. For example, after processing with mixed acid OJ(HF:NH₄F:CH₃COOH=2.1%:28.6%:23.6%) for 10 seconds, and with mixed acid(fluoric acid:nitric acid=1:200) for 5 seconds, the sample with platinumvapor-deposited is observed with the SEM (Scanning Electron Microscope)to measure the overlapping amount of the charge storage layer and thesource region.

As shown in FIG. 8, when the overlapping amount of the charge storagelayer and the source region is less than 40 nm, the varied amount of thethreshold voltage becomes smaller as the overlapping amount becomessmaller. The reason for this is considered to be that when theoverlapping amount becomes smaller, the increase of the inject holes tothe charge storage layer CSL gradually decreases, and the movement inthe transverse direction of the electrons and the holes locally existingin the charge storage layer CSL decreases. When the overlapping amountof the charge storage layer and the source region is 40 nm or more,since the holes do not reach the source region Srm in the BTBT system,the variation of the threshold voltage is very small.

FIG. 9 shows a relation of an erasing time before the threshold voltagereaches an erase judgment voltage (−1.8 volts) at room temperature afterrewriting 10K times, and the overlapping amount of the charge storagelayer and the source region. Rewriting of 10K times is performedaccording to the writing and erasing conditions shown in FIG. 4, andmanufacturing and measuring methods, etc. of the sample are the same asindicated in the description of FIG. 8.

As shown in FIG. 9, as the overlapping amount of the charge storagelayer and the source region becomes smaller, the erasing time becomeslonger, and when the overlapping amount becomes smaller than 25 nm, theerasing time suddenly becomes long.

The variation of the threshold voltage of the memory cell when holdingat a high temperature in the write state shown in FIG. 8 and the erasingtime at room temperature of the memory cell after rewriting 10K timesshown in the FIG. 9 indicate that the overlapping amount of the chargestorage layer CSL and the source region Srm less than 40 nm, forexample, is considered to be appropriate (the range is not limitedthereto depending on other conditions). The range suitable for massproduction is from 10 to 30 nm, and the range with 25 nm as a centervalue is considered to be most suitable. For example, a memory cell MC1can be constituted to be 80 nm in the gate length (Lg) of the memorygate electrode MG, 50 nm in the overlapping amount (Lso) of the memorygate electrode MG and the source region Srm, 30 nm in the effectivechannel length (Lch) of the memory gate electrode MG, 20 to 40 nm in theetching amount (Let) of the charge storage layer CSL, and 10 to 30 nm inthe overlapping amount (Lono) of the charge storage layer CSL and thesource region Srm.

Next, an example of the method of manufacturing the split-gate typeMONOS memory cell according to Embodiment 1 will be described withreference to FIGS. 10 to 23. FIGS. 10 to 16 and FIGS. 18 to 23 are thecross-sectional view of main parts of the memory cell during themanufacturing process of the semiconductor device, showing the same partas the cross-sectional view of main parts of the memory cell shown inthe FIG. 3, and FIG. 17 is a graph chart showing the relation betweenthe etching amount of the charge storage layer, and the etching time.

First, for example, a semiconductor substrate 1 consisting of a p-typesingle crystal silicon (a thin flat board in an approximate circle shapeof a semiconductor called a semiconductor wafer in this stage) having aresistivity of approximately 1 to 10 Ω·cm is prepared. Next, on the mainsurface of the semiconductor substrate 1, a trench shaped deviceisolation portion SGI, the active region located to be surroundedthereby, and the like are formed. That is, after forming an isolationtrench in a specified position of the semiconductor substrate 1, aninsulating film consisting, for example, of a silicon oxide film isdeposited on the main surface of the semiconductor substrate 1, and theinsulating film is polished by the CMP (Chemical Mechanical Polishing)method and the like to leave the insulating film only in the isolationtrench to form a device isolation portion SGI.

Next, as shown in FIG. 10, a specified impurity is selectivelyintroduced to a specified part of the semiconductor substrate 1 with aspecified energy by ion-implant method and the like to form embeddedn-well NW and p-well PW. Next, a p-type impurity such as boron ision-implanted to the main surface of the semiconductor substrate 1 toform the p-type semiconductor region 5 for forming the channel of thenMIS (Qnc) for selection. The implanting energy of the p-type impurityion in this process is approximately 20 keV and the dose isapproximately 1.5×10¹³ cm⁻², for example.

Next, by performing an oxidation treatment to the semiconductorsubstrate 1, the gate insulating film 4 with a thickness of 1 to 5 nmformed of, e.g., a silicon oxide film is formed on the main surface ofthe semiconductor substrate 1. Next, a first conductor film formed of apolycrystalline silicon film having an impurity concentration ofapproximately 2×10²⁰ cm⁻³ is deposited on the main surface of thesemiconductor substrate 1. The first conductor film is formed by the CVD(Chemical Vapor Deposition) method, and has a thickness of approximately150 to 250 nm, for example. Next, the first conductor film is processedby using a resist pattern as a mask to form the selection gate electrodeCG. The gate length of the selection gate electrode CG is approximately100 to 200 nm, for example.

Next, as shown in FIG. 11, ion-implanting an n-type impurity, such asarsenic and phosphorus, to the main surface of the semiconductorsubstrate 1 using the selection gate electrode CG and the resist patternas a mask to form an n-type semiconductor region 7 for forming thechannel of the nMIS for the memory. The implanting energy of the n-typeimpurity ion in this process is approximately 25 keV and the dose isapproximately 6.5×10¹² cm⁻², for example.

Next, the insulating film 6 b formed of a silicon oxide film, the chargestorage layer CSL formed of a silicon nitride film, and the insulatingfilm 6 t formed of a silicon oxide film are deposited in turn on themain surface of the semiconductor substrate 1, for example. Theinsulating film 6 b is formed by the thermal oxidation method, and has athickness of approximately 1 to 10 nm, the charge storage layer CSL isformed by the CVD method, and has a thickness of approximately 5 to 20nm, and the insulating film 6 t is formed by the CVD method, and has athickness of 5 to 15 nm, for example. Therefore, the thicknesses of theinsulating films 6 b, 6 t, and the charge storage layer CSL areapproximately 11 to 45 nm, for example. The insulating films 6 b, 6 t,and the charge storage layer CSL function as a gate insulating film ofthe nMIS (Qnm) for the memory to be formed later in addition to having acapability for holding an electric charge. In addition, the insulatingfilms 6 b, 6 t, and the charge storage layer CSL have characteristicsthat the potential barrier height of the middle layer is low compared tothe potential barrier height of the lower and upper layers.

The insulating film 6 t can be formed by thermally oxidizing an upperpart of the charge storage layer CSL, for example, and a high withstandvoltage film can be formed. In this case, the thickness of the depositedfilm of the charge storage layer CSL only has to be greater than theabove-mentioned value. In addition, although the insulating film 6 t canbe formed only by the thermal oxidation of the upper part of the chargestorage layer CSL, the growth rate of the insulating film 6 t (growthrate of a silicon oxide film obtained by thermal oxidation of a siliconnitride film) is relatively slow; therefore, after depositing a siliconoxide film with a thickness of approximately 6 nm on the charge storagelayer CSL, approximately 1 nm of the upper layer of the charge storagelayer CSL can be oxidized to form an insulating film 6 t with the totalthickness of 7 nm. Thus, the high withstand voltage film can also beformed.

The configurations of each film (insulating film 6 b, charge storagelayer CSL, and insulating film 6 t) constituting the insulating films 6b, 6 t, and the charge storage layer CSL change depending on usage ofthe semiconductor device to manufacture, only typical configurations andvalues are shown herein, and the above-mentioned configurations andvalues are not limitative.

Next, as shown in FIG. 12, a second conductor film 8 a formed of apolycrystalline silicon film having an impurity concentration ofapproximately 2×10²⁰ cm⁻³ is deposited on the main surface of thesemiconductor substrate 1. The second conductor film 8 a is formed bythe CVD method, and has a thickness of approximately 50 to 150 nm, forexample.

Next, as shown in FIG. 13, by etching back the second conductor film 8 awith an anisotropic dry etching method, sidewalls 8 are formed on bothside surfaces of the selection gate electrode CG via the insulatingfilms 6 b, 6 t, and the charge storage layer CSL. Although no shown, thesecond conductor film 8 a is processed by using a resist pattern as amask, and a drawing part is formed in an area to form a contact hole tobe connected with the memory gate electrode later. In addition, in theprocess of forming the sidewall 8, the second conductor film 8 a isetched back with the insulating film 6 t as an etching stopper layer,but etching conditions with a low damage is preferably configured toprevent the insulating film 6 t and the charge storage layer CSLthereunder from being damaged by the etch back. Damage to the insulatingfilm 3 t and the charge storage layer CSL will deterioratecharacteristics of the memory cell such as charge storagecharacteristics.

Next, as shown in FIG. 14, with a resist pattern as a mask, the sidewall8 exposed therefrom is etched to form the memory gate electrode MGincluding the sidewall 8 on one of the side walls of the selection gateelectrode CG. The gate length of the memory gate electrode MG isapproximately 50 to 150 nm, for example.

Since the gate length of the memory gate electrode MG can be determinedby the thickness of the deposited film of the second conductor film 8 a,the gate length of the memory gate electrode MG is adjusted by adjustingthe thickness of the deposited film of the second conductor film 8 a.The gate length of the memory gate electrode MG can be shorter by makingthe thickness of the deposited film of the second conductor film 8 asmaller, and the gate length of the memory gate electrode MG can belonger by making the thickness of the deposited film of the secondconductor film 8 a greater, for example. The thickness of the depositedfilm of the second conductor film 8 a is preferably approximately 50 to150 nm due to channel control characteristics and writing/erasingcharacteristics of the memory cell MC1 having a relation of trade-off.Furthermore, when the gate length of the selection gate electrode CG isapproximately 200 nm, the thickness of the deposited film of the secondconductor film 8 a is preferably about 50 to 100 nm. Thereby, the gatelength of the memory gate electrode MG can be approximately 50 to 100nm.

Next, as shown in FIG. 15, leaving a part of the insulating films 6 b, 6t, and the charge storage layer CSL between the selection gate electrodeCG and the memory gate electrode MG, and between the semiconductorsubstrate 1 and the memory gate electrode MG, the insulating films 6 b,6 t, and the charge storage layer CSL in the other area are selectivelyetched.

Next, as shown in FIG. 16, the charge storage layer CSL is side etchedwith an isotropic wet etching method to adjust the overlapping amount ofthe charge storage layer CSL and a source region. For example, thecharge storage layer CSL can be etched using heated phosphoric acid ofapproximately 160° C., and the etching amount is controlled by theetching time. FIG. 17 shows the relation between the etching amount ofthe charge storage layer (silicon nitride film) and the etching time.FIG. 17 indicates that the etching amount is proportional to the etchingtime, and therefore, the etching amount of the charge storage layer canbe controlled by the etching time.

Next, as shown in FIG. 18, after forming a resist pattern having an endthereof located on the top surface of the selection gate electrode CGand covering a part of the selection gate electrode CG on the oppositeside of the memory gate electrode MG, an n-type impurity such as arsenicis ion-implanted to the main surface of the semiconductor substrate 1using the selection gate electrode CG, the memory gate electrode MG, andthe resist pattern as a mask to form the n⁻-type semiconductor region 2as on the main surface of the semiconductor substrate 1 in a selfalignment manner to the memory gate electrode MG. The implanting energyof the impurity ion in this process is approximately 5 keV and the doseis approximately 1×10¹⁵ cm⁻², for example.

Next, after forming a resist pattern having an end thereof located onthe top surface of the selection gate electrode CG and covering a partof the selection gate electrode CG on the memory gate electrode MG sideand the memory gate electrode MG, an n-type impurity such as arsenic ision-implanted to the main surface of the semiconductor substrate 1 usingthe selection gate electrode CG, the memory gate electrode MG, and theresist pattern as a mask to form the n⁻-type semiconductor region 2 adon the main surface of the semiconductor substrate 1 in a self alignmentmanner to the selection gate electrode CG. The implanting energy of then-type impurity ion in this process is approximately 7 keV and the doseis approximately 1×10¹⁵ cm⁻², for example.

The n⁻-type semiconductor region 2 as was formed first, and then then⁻-type semiconductor region 2 ad was formed herein, but the n⁻-typesemiconductor region 2 ad can be formed first, and then the n⁻-typesemiconductor region 2 as can be formed. In addition, the n⁻-typesemiconductor regions 2 as and 2 ad can be formed simultaneously. Inaddition, after ion-implant of the n-type impurity to form the n⁻-typesemiconductor region 2 ad, a p-type impurity such as boron can beion-implanted to the main surface of the semiconductor substrate 1 toform the p-type semiconductor region to surround the lower part of then⁻-type semiconductor regions 2 as and 2 ad. The implanting energy ofthe p-type impurity ion is approximately 20 keV and the dose isapproximately 2.5×10¹³ cm², for example.

The memory cell MC1 according to Embodiment 1 generates holes using,what is called, the interband tunneling phenomenon in an end of then⁻-type semiconductor region 2 as when erasing. The efficiency forproducing holes with this phenomenon depends on the impurityconcentration (charge density of the impurity) on the n⁻-typesemiconductor region 2 as side, and a certain impurity concentration issuitable for generation of the holes. Therefore, when forming then⁻-type semiconductor region 2 as, phosphorus of 1×10¹³ to 1×10¹⁴ cm⁻²in dose as well as arsenic is ion-implanted to form an impurityconcentration region suitable for generation of holes on the side (end)of the impurity region formed with arsenic. That is, when arsenic andphosphorus are ion-implanted, phosphorus diffuses more easily thanarsenic in the transverse direction (direction parallel to the mainsurface of the semiconductor substrate 1); therefore, an area with a lowimpurity concentration is formed in the end of the n⁻-type semiconductorregion 2 as. Thereby, holes can be efficiently generated.

Next, as shown in FIG. 19, after depositing an insulating film with athickness of approximately 80 nm formed of, e.g., a silicon oxide filmwith the plasma CVD method on the main surface of the semiconductorsubstrate 1, the obtained insulating film is etched back with ananisotropic dry etching method to form sidewalls 9 on one side of theselection gate electrode CG and on one side of the memory gate electrodeMG. The spacer length of the sidewalls 9 is approximately 60 nm, forexample. Thereby, the exposed side of the gate insulating film 6 betweenthe selection gate electrode CG and the semiconductor substrate 1, andthe exposed side of the insulating films 6 b, 6 t, and the chargestorage layer CSL between the memory gate electrode MG and thesemiconductor substrate 1 can be covered by sidewalls 9.

Next, as shown in FIG. 20, an n-type impurity such as arsenic andphosphorus is ion-implanted to the main surface of the semiconductorsubstrate 1 by using the sidewalls 9 as a mask to form the n⁺-typesemiconductor region 2 b on the main surface of the semiconductorsubstrate 1 in a self alignment manner to the selection gate electrodeCG and the memory gate electrode MG. The implanting energy of the n-typeimpurity ion in this process is approximately 50 keV and the dose isapproximately 4×10¹⁵ cm⁻², for example, and the implanting energy ofphosphorous ion is approximately 40 keV and the dose is approximately5×10¹³ cm⁻², for example. Thereby, the drain region Drm including then⁻-type semiconductor region 2 ad and the n⁺-type semiconductor region 2b, and the source region Srm including the n⁻-type semiconductor region2 as and the n⁺-type semiconductor region 2 b are formed.

Next, as shown in FIG. 21, the semiconductor substrate 1 is heat-treatedto extend the source region Srm to the area under the memory gateelectrode MG to determine the overlapping amount of the charge storagelayer CSL and the source region Srm. For example, spike annealing at1,000° C. to the semiconductor substrate 1 for 10 seconds can extend thesource region Srm by approximately 50 nm.

Next, as shown in FIG. 22, a cobalt silicide (CoSi₂) layer 10 is formedin a self alignment manner, such as with the Salicide (Salicide: SelfAlign silicide) process on the top surface of the selection gateelectrode CG and the memory gate electrode MG, and on the top surface ofthe n⁺-type semiconductor region 2 b. First, a cobalt film is depositedby the sputtering method on the main surface of the semiconductorsubstrate 1. Next, by performing heat treatment using the RTA (RapidThermal Annealing) method to the semiconductor substrate 1, the cobaltfilm and the polycrystalline silicon film constituting the selectiongate electrode CG and the polycrystalline silicon film constituting thememory gate electrode MG, and the cobalt film and the single crystalsilicon constituting the semiconductor substrate 1 (n⁺-typesemiconductor region 2 b) are reacted to form a cobalt silicide layer10. Then, the unreacted part of the cobalt film is removed. The cobaltsilicide layer 10 that is formed can reduce the contact resistance ofthe cobalt silicide layer 10 and the plug and so forth formed thereon,and can reduce the resistance of the selection gate electrode CG, thememory gate electrode MG, the source region Srm, and the drain regionDrm.

Next, as shown in FIG. 23, an interlayer insulation film 11 formed of,for example, a silicon nitride film 11 a and a silicon oxide film 11 bis formed with the CVD method on the main surface of the semiconductorsubstrate 1. Next, after forming the contact hole CNT in the interlayerinsulation film 11, the plug PLG is formed in the contact hole CNT. Theplug PLG has, for example, a relatively thin barrier film formed of astacked film of titanium and titanium nitride, and a relatively thickconductor film including tungsten or aluminum formed to be wrapped bythe barrier film. Then, the first layer interconnection M1 including,for example, tungsten, aluminum, and copper is formed on the interlayerinsulation film 11 to obtain the substantially complete memory cell MC1shown in FIG. 3. After this process, the semiconductor device ismanufactured through conventional manufacturing processes of thesemiconductor devices.

Thus, according to Embodiment 1, the charge storage layer CSL thatintervenes between the memory gate electrode MG and the semiconductorsubstrate 1 of the nMIS (Qnm) for the memory is formed shorter than thegate length of the memory gate electrode MG or the insulating films 6 band 6 t located on and under the charge storage layer CSL to control theoverlapping amount of the charge storage layer CSL, and the sourceregion Srm to be less than 40 nm (preferably in the range from 10 to 30nm), to obtain a smaller varied amount of the threshold voltage when thememory cell MC1 is held at a high temperature in the writing state.Thereby, the data retention characteristic of the split-gate type MONOSmemory cell MC1 can be improved.

Embodiment 2

In Embodiment 2, an example of a split-gate type MONOS memory cell willbe described that has a structure different from the one in Embodiment 1that can control the overlapping amount of the charge storage layer andthe source region. A method of manufacturing the split-gate type MONOSmemory cell according to Embodiment 2 will be described with referenceto FIGS. 24 to 30. FIGS. 24 to 29 are cross-sectional view of main partsof the memory cell during the manufacturing process of the semiconductordevice; and FIG. 30 is a graph chart showing the characteristics forholding at a high temperature of the memory cell in the writing stateafter rewriting 10K times. The array configuration and operatingconditions of the split-gate type MONOS memory cell according toEmbodiment 2 are the same as that of Embodiment 1 mentioned above. Themanufacturing processes before forming a selection gate electrode CG ofan nMIS (Qnc) for selection, and a memory gate electrode MG of an nMIS(Qnm) for a memory are the same as the manufacturing processes of thememory cell MC1 (FIG. 15) of Embodiment 1 mentioned above, anddescriptions therefor are omitted.

After the manufacturing process described using FIG. 15, as shown inFIG. 24, an insulating film 21 with a thickness of approximately 50 nmformed of a silicon oxide film is deposited with the CVD method on themain surface of the semiconductor substrate 1.

Next, as shown in FIG. 25, the insulating film 21 is etched back with ananisotropic dry etching method, and the sidewall formed on one side ofthe selection gate electrode CG is removed to form a sidewall 22 on oneside of the memory gate electrode MG. The spacer length of the sidewalls22 is approximately 20 to 40 nm, for example.

Next, as shown in FIG. 26, an n⁻-type semiconductor region 2 as isformed on the main surface of the semiconductor substrate 1 in aself-alignment manner to the memory gate electrode MG, and an n⁻-typesemiconductor region 2 ad is formed on the main surface of thesemiconductor substrate 1 in a self alignment manner to the selectiongate electrode CG. After an n-type impurity for forming the n⁻-typesemiconductor regions 2 as and 2 ad is ion-implanted, a p-type impuritysuch as boron can be ion-implanted to the main surface of thesemiconductor substrate 1 to form a p-type semiconductor region so as tosurround the lower part of the n⁻-type semiconductor region 2 as and 2ad.

Next, as shown in FIG. 27, after depositing an insulating film with athickness of approximately 80 nm formed of, e.g., a silicon oxide filmwith the plasma CVD method on the main surface of the semiconductorsubstrate 1, the obtained insulating film is etched back with ananisotropic dry etching method to form sidewalls 9 on one side of theselection gate electrode CG and on one side of the memory gate electrodeMG. The spacer length of the sidewalls 9 is approximately 60 nm, forexample.

Next, as shown in FIG. 28, an n-type impurity such as arsenic andphosphorus is ion-implanted to the main surface of the semiconductorsubstrate 1 by using the sidewalls 9 as a mask to form an n⁺-typesemiconductor region 2 b on the main surface of the semiconductorsubstrate 1 in a self alignment manner to the selection gate electrodeCG and the memory gate electrode MG. Thereby, a drain region Drmincluding the n⁻-type semiconductor region 2 ad and the n⁺-typesemiconductor region 2 b, and a source region Srm including the n⁻-typesemiconductor region 2 as and the n⁺-type semiconductor region 2 b areformed.

Next, as shown in FIG. 29, the semiconductor substrate 1 is heat-treatedto extend the source region Srm to the area under the memory gateelectrode MG to determine the overlapping amount of the charge storagelayer CSL and the source region Srm. The overlapping amount can beadjusted with the spacer length of the sidewall 22.

Then, in the same manner as Embodiment 1 mentioned above, after forming,e.g., a cobalt silicide layer 10 in a self alignment manner on the topsurface of the selection gate electrode CG and the memory gate electrodeMG, and on the top surface of the n⁺-type semiconductor region 2 b, aninterlayer insulation film 11 is formed with the CVD method on the mainsurface of the semiconductor substrate 1. Next, after forming a contacthole CNT in the interlayer insulation film 11, a plug PLG is formed inthe contact hole CNT. Then, a first layer interconnection M1 is formedon the interlayer insulation film 11 to obtain a substantially completememory cell MC2.

FIG. 30 shows the relation between the varied amount of the thresholdvoltage of the memory cell, and the overlapping amount of the chargestorage layer and the source region when a high temperature is held inthe write state for 1 hour after rewriting 10K times. Rewriting of 10Ktimes is performed according to the writing and erasing conditions shownin FIG. 4, and manufacturing and measuring methods, etc. of the sampleare the same as indicated in the description of FIG. 8.

As shown in FIG. 30, when the overlapping amount of the charge storagelayer and the source region is less than 40 nm, the varied amount of thethreshold voltage becomes smaller as the overlapping amount becomessmaller. When the overlapping amount of the charge storage layer and thesource region is 40 nm or more, since the holes do not reach the sourceregion Srm in the BTBT system, the variation of the threshold voltage isvery small.

From the variation of the threshold voltage of the memory cell whenholding at a high temperature in the write state shown in FIG. 30, when,for example, the overlapping amount (Lso) of the memory gate electrodeMG and the source region Srm is 10 to 30 nm, the etching amount (Let) ofthe charge storage layer CSL is 0 nm, and the overlapping amount (Lono)of the charge storage layer CSL and the source region Srm is 10 to 30nm, an appropriate spacer length of the sidewall 22 is considered to bein the range from 20 to 40 nm.

Thus, according to Embodiment 2, the sidewall 22 having the spacerlength of approximately 20 to 40 nm is formed on the side wall of thememory gate electrode MG of the nMIS (Qnm) for the memory to control theoverlapping amount of the charge storage layer CSL and the source regionSrm to be less than 40 nm (preferably in the range from 10 to 30 nm) toobtain a smaller varied amount of the threshold voltage when the memorycell MC2 is held at a high temperature in the writing state. Thereby,the data retention characteristic of the split-gate type MONOS memorycell MC2 can be improved.

Embodiment 3

In Embodiment 3, an example of a split-gate type MONOS memory cell thatcan improve the characteristics for holding at room temperature in anerase state by adjusting the effective channel length of a memory gateelectrode of an nMIS for a memory will be described using FIGS. 31 to35. FIGS. 31 and 32 are cross-sectional view of main parts of a firstexample of the split-gate type MONOS memory cell according to Embodiment3; FIGS. 33 and 34 are cross-sectional view of main parts of a secondexample of the split-gate type MONOS memory cell according to Embodiment3; and FIG. 35 is a graph chart showing the characteristics for holdingat room temperature of the memory cell in the erase state afterrewriting 10K times. The array configuration and operating conditions ofthe split-gate type MONOS memory cell according to Embodiment 3 are thesame as that of Embodiment 1 mentioned above.

First, the first example of the method of manufacturing the split-gatetype MONOS memory cell according to Embodiment 3 will be described withreference to FIGS. 31 and 32. The manufacturing processes before forminga selection gate electrode CG of an nMIS (Qnc) for selection, and amemory gate electrode MG of an nMIS (Qnm) for a memory are the same asthe manufacturing processes of the memory cell MC1 (FIG. 15) ofEmbodiment 1 mentioned above, and descriptions therefor are omitted.

After the manufacturing process described using FIG. 15, as shown inFIG. 31, a charge storage layer CSL is side etched with an isotropic wetetching method to adjust the overlapping amount of the charge storagelayer CSL and a source region. The etching amount (Let) of the chargestorage layer CSL is 30 to 50 nm (20 to 40 nm for the memory cell MC1 ofEmbodiment 1 mentioned above). Next, an n⁻-type semiconductor region 2as is formed on the main surface of the semiconductor substrate 1 in aself alignment manner to the memory gate electrode MG, and an n⁻-typesemiconductor region 2 ad is formed on the main surface of thesemiconductor substrate 1 in a self alignment manner to the selectiongate electrode CG. After an n-type impurity forming the n⁻-typesemiconductor regions 2 as and 2 ad are ion-implanted, a p-type impuritysuch as boron can be ion-implanted to the main surface of thesemiconductor substrate 1 to form a p-type semiconductor region tosurround the lower part of the n⁻-type semiconductor region 2 as and 2ad.

Next, after depositing an insulating film with a thickness ofapproximately 80 nm formed of, e.g., a silicon oxide film with theplasma CVD method on the main surface of the semiconductor substrate 1,the obtained insulating film is etched back with an anisotropic dryetching method to form sidewalls 9 on one side of the selection gateelectrode CG and on one side of the memory gate electrode MG. The spacerlength of the sidewalls 9 is approximately 60 nm, for example.

Next, an n-type impurity such as arsenic and phosphorus is ion-implantedto the main surface of the semiconductor substrate 1 by using thesidewalls 9 as a mask to form an n⁺-type semiconductor region 2 b on themain surface of the semiconductor substrate 1 in a self alignment mannerto the selection gate electrode CG and the memory gate electrode MG.Thereby, a drain region Drm including the n⁻-type semiconductor region 2ad and the n⁺-type semiconductor region 2 b, and the source region Srmincluding the n⁻-type semiconductor region 2 as and the n⁺-typesemiconductor region 2 b are formed.

Next, as shown in FIG. 32, the semiconductor substrate 1 is heat-treatedto extend the source region Srm to the area under the memory gateelectrode MG to determine the overlapping amount of the charge storagelayer CSL and the source region Srm and the effective channel length ofthe memory gate electrode MG. For example, spike annealing at 1,050° C.to the semiconductor substrate 1 for 10 seconds can extend the sourceregion Srm by approximately 60 nm.

Even when the overlapping amount (Lso) of the memory gate electrode MGand the source region Srm is 60 nm (50 nm for the memory cell MC1 ofEmbodiment 1 mentioned above), as mentioned above, since the etchingamount (Let) of the charge storage layer CSL is 30 to 50 nm (20 to 40 nmfor the memory cell MC1 of Embodiment 1 mentioned above), theoverlapping amount (Lono) of the charge storage layer CSL and the sourceregion Srm can be in the appropriate range of 10 to 30 nm and, at thesame time, the effective channel length (Lch) of the memory gateelectrode MG can be shortened. For example, a memory cell MC2 with thememory gate electrode MG of 80 nm in the gate length (Lg) can have theeffective channel length (Lch) of 20 nm in the memory gate electrode MG(30 nm for the memory cell MC1 of the Embodiment 1 mentioned above.)

Then, in the same manner as Embodiment 1 mentioned above, after forming,e.g., a cobalt silicide layer 10 in a self alignment manner on the topsurface of the selection gate electrode CG and the memory gate electrodeMG, and on the top surface of the n⁺-type semiconductor region 2 b, aninterlayer insulation film 11 is formed with the CVD method on the mainsurface of the semiconductor substrate 1. Next, after forming a contacthole CNT in the interlayer insulation film 11, a plug PLG is formed inthe contact hole CNT. Then, a first layer interconnection M1 is formedon the interlayer insulation film 11 to obtain a substantially completememory cell MC3 a.

Next, the second example of the method of manufacturing the split-gatetype MONOS memory cell according to Embodiment 3 will be described withreference to FIGS. 33 and 34. The manufacturing processes before formingthe selection gate electrode CG of the nMIS (Qnc) for selection, and thememory gate electrode MG of the nMIS (Qnm) for the memory are the sameas the manufacturing processes of the memory cell MC2 (FIG. 25) ofEmbodiment 2 mentioned above, and descriptions therefor are omitted.However, the gate length of the memory gate electrode MG is formedshorter, for example by approximately 10 nm, than that of the gateelectrode MG of the memory cell MC2 of Embodiment 2 mentioned above.

After the manufacturing process described using FIG. 25, as shown inFIG. 33, a sidewall 22 is formed only on one side of the memory gateelectrode MG. Then, the n⁻-type semiconductor region 2 as is formed onthe main surface of the semiconductor substrate 1 in a self alignmentmanner to the memory gate electrode MG, and the n⁻-type semiconductorregion 2 ad is formed on the main surface of the semiconductor substrate1 in a self alignment manner to the selection gate electrode CG. Afterthe n-type impurity forming the n⁻-type semiconductor regions 2 as and 2ad are ion-implanted, the p-type impurity such as boron can beion-implanted to the main surface of the semiconductor substrate 1 toform the p-type semiconductor region to surround the lower part of then⁻-type semiconductor regions 2 as and 2 ad.

Next, after depositing an insulating film with a thickness ofapproximately 80 nm formed of, e.g., a silicon oxide film with theplasma CVD method on the main surface of the semiconductor substrate 1,the obtained insulating film is etched back with an anisotropic dryetching method to form sidewalls 9 on one side of the selection gateelectrode CG and on one side of the memory gate electrode MG. The spacerlength of the sidewalls 9 is approximately 60 nm, for example.

Next, an n-type impurity such as arsenic and phosphorus is ion-implantedto the main surface of the semiconductor substrate 1 by using thesidewalls 9 as a mask to form the n⁺-type semiconductor region 2 b onthe main surface of the semiconductor substrate 1 in a self alignmentmanner to the selection gate electrode CG and the memory gate electrodeMG. Thereby, the drain region Drm including the n⁻-type semiconductorregion 2 ad and the n⁺-type semiconductor region 2 b, and the sourceregion Srm including the n⁻-type semiconductor region 2 as and then⁺-type semiconductor region 2 b are formed.

Next, as shown in FIG. 34, the semiconductor substrate 1 is heat-treatedto extend the source region Srm to the area under the memory gateelectrode MG to determine the overlapping amount of the charge storagelayer CSL and the source region Srm and the effective channel length ofthe memory gate electrode. For example, spike annealing at 1,000° C. tothe semiconductor substrate 1 for 10 seconds can extend the sourceregion Srm by approximately 50 nm. Thereby, the overlapping amount(Lono) of the charge storage layer CSL and the source region Srm can bein the appropriate range of 10 to 30 nm and, at the same time, theeffective channel length (Lch) of the memory gate electrode MG can beformed shorter, for example by approximately 10 nm, than the channellength (Lch) of the memory gate electrode MG of the memory cell MC2 ofEmbodiment 2 mentioned above.

Then, in the same manner as Embodiment 1 mentioned above, after forming,e.g., the cobalt silicide layer 10 in a self alignment manner on the topsurface of the selection gate electrode CG and the memory gate electrodeMG, and on the top surface of the n⁺-type semiconductor region 2 b, theinterlayer insulation film 11 is formed with the CVD method on the mainsurface of the semiconductor substrate 1. Next, after forming thecontact hole CNT in the interlayer insulation film 11, the plug PLG isformed in the contact hole CNT. Then, the first layer interconnection M1is formed on the interlayer insulation film 11 to obtain a substantiallycomplete memory cell MC3 b.

FIG. 35 shows the relation between the varied amount of the thresholdvoltage of the memory cell, and the effective channel length of the gateelectrode of the nMIS for the memory when the room temperature is heldin the erase state for 1,000 hours after rewriting 10K times. Rewritingof 10K times is performed according to the writing and erasingconditions shown in FIG. 4, and manufacturing and measuring methods, andthe like of the sample are the same as indicated in the description ofFIG. 8.

To make the variation of the threshold voltage of the memory cellsmaller when holding at room temperature in the erase state, the amountof electrons that exist in the inversion layer in the semiconductorsubstrate and that couple with holes in the charge storage layer via thedefect, produced by rewriting, of the insulating film on thesemiconductor substrate side must be reduced. Therefore, the apparentamount of holes is reduced by shortening the effective channel length ofthe memory gate electrode to obtain a smaller electric field in thelengthwise direction to the main surface of the semiconductor substrate.This reduces the amount of the electrons that couple with the holesdecreases, resulting in a smaller variation of the threshold voltage ofthe memory cell. In addition, since the BTBT system is used for erasing,the holes that determine the threshold voltage are locally existed anddistributed in the charge storage layer. Therefore, as shown in FIG. 35,a reduction of the effective channel length from 30 nm to 20 nm suddenlyreduced the threshold voltage. Therefore, an appropriate effectivechannel length of the memory gate electrode is considered to be 30 nm orless, for example (the range is not limited thereto depending on otherconditions). Moreover, a range suitable for mass production isconsidered to be 20 nm or less.

Thus, according to Embodiment 3, in the same manner as Embodiment 1 and2 mentioned above, the overlapping amount of the charge storage layerCSL and the source region Srm less than 40 nm (preferably in the rangefrom 10 to 30 nm) and the effective channel length (Lch) of the memorygate electrode MG not more than 30 nm (preferably not more than 20 nm)reduce the electric field in the direction vertical to the main surfaceof the semiconductor substrate 1 to cause fewer coupling of electronswith holes, resulting in the smaller varied amount of the thresholdvoltage when holding the memory cells MC3 a and the MC3 b at a hightemperature in the writing state and the smaller varied amount of thethreshold voltage when holding the memory cell at room temperature inthe erase state. Thereby, the data retention characteristic of thesplit-gate type MONOS memory cells MC3 a and MC3 b can be improved.

Embodiment 4

An example of the structure of an NROM memory cell according toEmbodiment 4 will be described with reference to FIGS. 36 to 43. TheNROM memory cell also has a problem in which, in the same manner as thesplit-gate type MONOS memory cell, a threshold voltage of a memory cellgradually decreases as the holding time passes as to characteristics forholding at a high temperature in the write state, and the thresholdvoltage of the memory cell gradually increases as the holding timepasses as to characteristics for holding at room temperature in theerase state. In Embodiment 4, the control method of the overlappingamount of a charge storage layer and a source region, which has beendescribed with the split-gate type MONOS memory cells of Embodiments 1and 2 mentioned above, is applied to the NROM memory cell. FIGS. 36 to40 are cross-sectional view of main parts of a first example of the NROMmemory cell according to Embodiment 4; FIG. 41 is a table summarizing anexample of conditions for applying the voltage to each part of thememory cell during write, erase, and read operations; and FIGS. 42 and43 are cross-sectional view of main parts of a second example of theNROM memory cell according to Embodiment 4.

The method of manufacturing the first example of the NROMMOS memory cellaccording to Embodiment 4 will be described with reference to FIGS. 36to 40.

First, as shown in FIG. 36, a semiconductor substrate 41 consisting of ap-type single crystal silicon (a thin flat board in an approximatecircle shape of a semiconductor called a semiconductor wafer in thisstage) having a resistivity of approximately 1 to 10 Ω·cm is prepared.Next, on the main surface of the semiconductor substrate 1, a trenchshaped device isolation portion SGI, for example, the active regionlocated to be surrounded thereby, etc. are formed. Subsequently, ap-type impurity is selectively introduced to a specified part of asemiconductor substrate 41 with a specified energy by ion implant etc.to form a p-well 42 having an impurity concentration of appropriately1×10¹⁷ cm³.

Next, by performing an oxidation treatment to the semiconductorsubstrate 41, an insulating film 43 b with a thickness of approximately4 nm formed of, e.g., a silicon oxide film is formed on the main surfaceof the semiconductor substrate 41. Next, a charge storage layer CSL1with a thickness of approximately 6 nm formed of, e.g., a siliconnitride film is deposited with the CVD method on the insulating film 43b, and a charge storage layer CSL2 with a thickness of approximately 5nm formed of, e.g., a silicon nitride film with oxygen is deposited onthe charge storage layer CSL1. Generally, although SiH₂C1 ₂ and NH₃ areused as source gasses in the CVD method to form a silicon nitride film,a silicon nitride film with a specified concentration of oxygen can beformed by adding an oxidizer (such as N₂O) to the source gases andcontrolling the flow rate of NH₃. Addition of oxygen can enlarge theband gap of the silicon nitride film. In the charge storage layer CSL2formed of the silicon nitride film with oxygen, the composition ratio ofoxygen to nitrogen is 1:1.

Next, an insulating film 43 t with a thickness of approximately 1 nmformed of, e.g., an oxide film is formed on the charge storage layerCSL2. The ISSG (In-Site Steam Generation) oxidation method is used informing the insulating film 43 t. Since the film thickness of the chargestorage layer CSL2 is reduced by oxidization in the ISSG oxidationmethod, when depositing the charge storage layer CSL2, the thickness ofthe deposited film of the charge storage layer CSL2 must be configured,taking the reduction of the film thickness by the oxidization intoconsideration beforehand. Thereby, a stacked insulating film comprisingthe insulating film 43 b, the charge storage layers CSL1, CSL2, and theinsulating film 43 t is formed.

Next, as shown in FIG. 37, a conductor film formed of a polycrystallinesilicon film with an impurity concentration of approximately 2×10²⁰ cm⁻³is deposited on the insulating film 43 t. The conductor film is formedby the CVD method, and has a thickness of approximately 150 nm, forexample. Subsequently, the conductor film is processed by using a resistpattern as a mask, and a gate electrode 44 is formed. Then, leaving apart of the insulating films 43 b and 43 t, and the charge storagelayers CSL1 and CSL2 between the gate electrode 44 and the semiconductorsubstrate 41, the insulating film 43 b and 43 t and the charge storagelayer CSL1 and CSL2 in the other area are selectively removed.

Next, as shown in FIG. 38, the charge storage layer CSL1 and CSL2 areside etched with an isotropic wet etching method to adjust theoverlapping amount of the charge storage layers CSL1 and CSL2, and thesource region. For example, the charge storage layer CSL1 and CSL2 canbe etched using heated phosphoric acid at approximately 160° C., and theetching amount is controlled by the etching time.

Next, as shown in FIG. 39, an n-type impurity such as arsenic ision-implanted to the main surface of the semiconductor substrate 41 byusing the gate electrode 44 as a mask to form an n⁺-type semiconductorregion on the main surface of the semiconductor substrate 41 in a selfalignment manner to the gate electrode 44. The implanting energy of theimpurity ion in this process is approximately 40 keV and the dose isapproximately 2×10¹⁵ cm⁻², for example. Subsequently, the n-typeimpurity ion-implanted is activated by heat treating for 60 seconds at atemperature of approximately 950° C., for example, to form source drainregions 45.

Next, as shown in FIG. 40, an interlayer insulation film 46 is formedwith the CVD method on the main surface of the semiconductor substrate41. Next, after forming contact holes 47 in the interlayer insulationfilm 46, plugs 48 is formed in the contact holes 47. Subsequently, afirst layer interconnection M1 including, for example, tungsten,aluminum, copper, and the like is formed on the interlayer insulationfilm 46 to obtain a substantially complete memory cell MC4 a. After thisprocess, the semiconductor device is manufactured through conventionalmanufacturing processes of the semiconductor devices.

FIG. 41 summarizes the voltages Vs and Vd applied to the source drainregion, the voltage Vmg applied to the gate electrode, and the voltageVsub applied to the semiconductor substrate of the NROM memory cellduring the write, erase, and read operations. The voltages shown in FIG.41 are examples of application conditions, and those are not limitedthereto, and modifications are possible if needed.

When a write operation by the SSI system and an erase operation by theBTBT system was performed to the memory cell MC4 a under the applicationconditions of each voltage shown in FIG. 41, the variation of thethreshold voltage of the memory cell MC4 a was smaller than thevariation of the threshold voltage of the memory cell with theoverlapping amount larger than 40 nm of the charge storage layers CSL1and CSL2, and the source drain region 45.

Next, the method of manufacturing the second example of the NROM memorycell according to Embodiment 4 will be described with reference to FIGS.42 and 43. The manufacturing processes before forming the gate electrode44 are the same as the manufacturing process of the memory cell MC4 a(FIG. 37) mentioned above, and descriptions therefor are omitted.

After the manufacturing process described using FIG. 37, as shown inFIG. 42, an insulating film with a thickness of approximately 20 nmformed of, e.g., a silicon oxide film is deposited with the CVD methodon the main surface of the semiconductor substrate 41. Then, theinsulating film is etched back with an anisotropic dry etching method toform sidewalls 49 on the side of the gate electrode 44. The spacerlength of the sidewalls 49 is approximately 20 nm, for example.

Next, the n-type impurity such as arsenic is ion-implanted to the mainsurface of the semiconductor substrate 1 by using the gate electrode 44as a mask to form the n⁺-type semiconductor region on the main surfaceof the semiconductor substrate 41 in a self alignment manner to the gateelectrode 44. The implanting energy of the impurity ion in this processis approximately 40 keV and the dose is approximately 2×10¹⁵ cm⁻², forexample. Subsequently, the n-type impurity ion-implanted is activated byheat treating for 60 seconds at a temperature of approximately 950° C.to form a source drain regions 45.

Next, as shown in FIG. 43, an interlayer insulation film 46 is formedwith the CVD method on the main surface of the semiconductor substrate41. Then, after forming the contact holes 47 in the interlayerinsulation film 46, the plugs 48 are formed in the contact holes 47.Subsequently, the first layer interconnection M1 including, for example,tungsten, aluminum copper, and the like is formed on the interlayerinsulation film 46 to obtain a substantially complete memory cell MC4 b.After this process, the semiconductor device is manufactured throughconventional manufacturing processes of the semiconductor devices.

When a write operation by the SSI system and an erase operation by theBTBT system were performed to the memory cell MC4 b under theapplication conditions of each voltage shown in FIG. 41, in the samemanner as the memory cell MC4 a, the variation of the threshold voltageof the memory cell MC4 b was smaller than the variation of the thresholdvoltage of the memory cell with the overlapping amount larger than 40 nmof the charge storage layer and the source drain region.

Thus, according to Embodiment 4, the charge storage layer CSL1 and CSL2that intervene between the gate electrode 44 and the semiconductorsubstrate 1 are formed shorter than the gate length of the gateelectrode 44, or the insulating films 43 b and 43 t located on and underthe charge storage layers CSL1 and CSL2, or the sidewalls 49 having thespacer length of approximately 20 to 40 nm are formed on the side wallsof the gate electrode 44 to control the overlapping amount of the chargestorage layer CSL1 and CSL2, and the source region Srm to be less than40 nm (preferably in the range from 10 to 30 nm) to obtain a smallervaried amount of the threshold voltage when the memory cells MC4 a andthe MC4 b are held at a high temperature in the writing state, and asmaller varied amount of the threshold voltage when holding the memorycells MC4 a and the MC4 b at room temperature in the erase state.Thereby, the data retention characteristic of the NROM memory cells MC4a and MC4 b can be improved.

In the foregoing, the invention made by the inventors of the presentinvention has been concretely described based on the embodiments.However, it is needless to say that the present invention is not limitedto the foregoing embodiments and various modifications and alterationscan be made within the scope of the present invention.

The present invention can be applied to a semiconductor memory having anonvolatile memory cell that stores an electric charge in an insulatingfilm such as a nitride film.

The invention claimed is:
 1. A method of forming a nonvolatilesemiconductor device, comprising: (a) forming a first gate insulatingfilm on a main surface of a first semiconductor region having firstconductivity type and being formed in a semiconductor substrate; (b)forming a first gate electrode on the first gate insulating film, thefirst gate electrode having a first side surface and a second sidesurface opposing to each other in a first direction; (c) forming asecond gate insulating film on the first side surface of the first gateelectrode and on the main surface of the first semiconductor region, thesecond gate insulating film including a bottom-layer insulating film, acharge storage layer formed on the bottom-layer insulating film andhaving a capability of accumulating charges, and a top-layer insulatingfilm formed on the charge storage layer; (d) forming a second gateelectrode over the first side surface of the first gate electrode andover the main surface of the first semiconductor region, via the secondgate insulating film; (e) selectively removing the second gateinsulating film on the main surface of the first semiconductor regionwhile keeping the second gate insulating film interposed between thesecond gate electrode and the main surface of the first semiconductorregion; (f) etching the second gate insulating film kept between thesecond gate electrode and the main surface of the first semiconductorregion in order to form the etched charge storage layer; (g) introducingfirst impurities having a second conductivity type, opposite the firstconductivity type, in the first semiconductor region in a self-alignedmanner to the second gate electrode in order to form a secondsemiconductor region; and (h) annealing the semiconductor substrate toextend the second semiconductor region to an area under the second gateelectrode, wherein the etched charge storage layer has a first portionwhich overlaps the second semiconductor region and a second portionwhich does not overlap the second semiconductor region, the firstportion and the second portion being located next to each other in thefirst direction, wherein the etched charge storage layer formed betweenthe second gate electrode and the main surface of the firstsemiconductor region is shorter than the second gate electrode in thefirst direction, wherein the second semiconductor region includes, inthe first direction, a first region overlapping with the etched chargestorage layer formed between the second gate electrode and the mainsurface of the first semiconductor region and a second region notoverlapping with the etched charge storage layer formed between thesecond gate electrode and the main surface of the first semiconductorregion, and wherein the first portion includes the first region.
 2. Themethod of forming a nonvolatile semiconductor device, according to claim1, wherein a length of the first region is less than 40 nm.
 3. Themethod of forming a nonvolatile semiconductor device, according to claim2, wherein the first region is in a range of 10 to 30 nm.
 4. The methodof forming a nonvolatile semiconductor device according to claim 1,wherein holes generated at an edge portion of the second semiconductorregion by an interband tunneling phenomenon are injected into the etchedcharge storage layer.
 5. The method of forming a nonvolatilesemiconductor device according to claim 1, comprising the followingsteps between the steps (b) and (c): (i) forming a third semiconductorregion by ion-implanting a second impurities having the secondconductivity type in the first semiconductor region.
 6. The method offorming a nonvolatile semiconductor device according to claim 5, whereinelectrons generated between the first semiconductor region and the thirdsemiconductor region are injected into the etched charge storage layer.7. The method of forming a nonvolatile semiconductor device according toclaim 1, wherein the step (d) includes the steps of: (d1) forming afirst conductor film on the second gate insulating film, and (d2)performing anisotropic dry etching to the first conductor film andforming a sidewall, wherein the second gate electrode is formed of thesidewall.
 8. The method of forming a nonvolatile semiconductor deviceaccording to claim 1, wherein in the step (f), the charge storage layeris etched in isotropic wet etching method.
 9. The method of forming anonvolatile semiconductor device according to claim 1, wherein thecharge storage layer is formed of a silicon nitride film.
 10. A methodof forming a nonvolatile semiconductor device, comprising: (a) forming agate insulating film formed on a main surface of a first semiconductorregion, having first conductivity type, formed in a semiconductorsubstrate, the gate insulating film includes a bottom-layer insulatingfilm, a charge storage layer formed on the bottom-layer insulating filmand having a capability of accumulating charges, and a top-layerinsulating film formed on the charge storage layer; (b) forming a firstconductor film on the gate insulating film, (c) patterning the firstconductor film in order to form a gate electrode having a first sidesurface and a second side surface opposing each other in a firstdirection, (d) removing the gate insulating film exposed from the gateelectrode while keeping the gate insulating film between the gateelectrode and the main surface of the first semiconductor region, (e)etching the gate insulating film kept between the gate electrode and themain surface of the first semiconductor region in order to form theetched charge storage layer; (f) introducing first impurities having asecond conductivity type, opposite the first conductivity type, in thefirst semiconductor region at the first surface side of the gateelectrode in order to form a second semiconductor region; and (g)annealing the semiconductor substrate to extend the second semiconductorregion to an area under the gate electrode, wherein the etched chargestorage layer formed between the gate electrode and the main surface ofthe first semiconductor region is shorter than the gate electrode in thefirst direction, wherein the etched charge storage layer has a firstportion which overlaps the second semiconductor region and a secondportion which does not overlap the second semiconductor region, thefirst portion and the second portion being located next to each other inthe first direction, wherein the first semiconductor region includes, inthe first direction, a first region overlapping with the etched chargestorage layer formed between the gate electrode and the main surface ofthe first semiconductor region and a second region not overlapping withthe etched charge storage layer formed between the gate electrode andthe main surface of the first semiconductor region, and wherein thefirst portion includes the first region.
 11. The method of forming anonvolatile semiconductor device according to claim 10, in the step (e),wherein the charge storage layer is etched in isotropic wet etchingmethod.
 12. The method of forming a nonvolatile semiconductor deviceaccording to claim 10, wherein the charge storage layer is formed of asilicon nitride film.